The present invention generally relates to a method for forming sidewall spacers for insulating polysilicon gates and devices formed and more particularly, relates to a method for forming dielectric sidewall spacers with square shoulders on polycide gates for eliminating electrical shorting problems between the polysilicon gate and source/drain silicide in the semiconductor structure and devices fabricated by the method.
Modern semiconductor devices are built on semi-conducting substrates such as silicon substrates that have P+ and N+ type doped regions in the substrates as basic elements of the device. These doped regions must be connected in a specific configuration to form a desired circuit. The circuit needs to be accessible to the outside world through conducting pads for testing and through bonding into a packaged chip. To form a semiconductor circuit, at least one layer of a conducting material such as metal must be deposited and patterned to form contacts and interconnects between the different regions of the chip. For instance, in a typical semiconductor fabrication process, a silicon wafer is first covered with an insulating layer and then, patterned and etched for contact openings in the insulating layer. A conductive material is then deposited and defined to form contact plugs and interconnecting leads.
On top of the silicon wafer, semiconductor gates are normally formed of a polysilicon material with a thin gate oxide layer formed in-between the polysilicon gate and the silicon substrate. A typical semiconductor gate structure 10 is shown in FIGS. 1A and 1B. In order to insulate the polysilicon gate 12, a silicon oxide layer 14 or any other dielectric material layer such as silicon nitride or silicon oxynitride can also be used. A thick silicon oxide layer of several thousand angstrom thickness can be deposited by a rapid thermal chemical vapor deposition (RTCVD) technique. In the process of forming such sidewall spacers 16 from the dielectric layer 14, it is important that the material deposited, i.e. silicon oxide, must have both a high deposition rate such that a thick layer can be deposited in a short period of time and also a good conformability such that the polysilicon gate can be completely covered. For instance, when silicon oxide is deposited, the TEOS (tetra-ethoxy-silane) chemistry can be used at a high deposition temperature of 800xc2x0 C. for achieving a deposition rate of about 1000 xc3x85/min. Such a high deposition rate would satisfy a throughput requirement for the semiconductor device. The high deposition temperature limits such deposition process to the front end of the fabrication process wherein metal wiring layers are not involved.
After the conformal deposition of the silicon oxide layer 14 to approximately 5000xcx9c8000 xc3x85 thickness, a reactive ion etching (RIE) method is conventionally used to pattern the gate sidewall spacers 16. The RIE technique is chosen since the anisotropic plasma used in the technique is effective in forming the sidewall spacers 16 on the gate 12. In the RIE technique, positive plasma ions in a parallel-plate RF reactor are used to provide a source of energetic particle bombardment for the etched surface, producing vertical edges in the etched film with negligible undercutting. The ion bombardment increases the reaction rate of spontaneously occurring processes and prompts reactions which do not occur without radiation. In a typical reactive ion etching system, the wafers are placed on the powered electrode of a parallel-plate RF reactor wherein horizontal surfaces are subjected to both reactant species and impinging ions, while vertical sidewalls are only subjected to reactive species.
In the conventional method of patterning sidewall spacers by the reactive ion etching method, it has been discovered that the plasma ions bombarded during the etching process damage the silicon surface at the source/drain area that will enhance dark current (or leakage current) and impact the signal/noise ratio of a photoelectronic device. As shown in FIG. 1B, a surface layer 18 of the silicon substrate 20 in the source/drain area 22, 24 is it frequently damaged by the plasma ions and severely effects the reliability of the device fabricated.
A method for fabricating a conventional sidewall spacer on a polysilicon gate structure is shown in FIGS. 1Axcx9c1E. FIGS. 1A and 1B show a polysilicon gate formation and LDD implant, respectively. For instance, in FIG. 1A, the semiconductor structure 10 is first formed on a silicon substrate 12 a thin gate oxide layer 14 having a thickness of less than 200 xc3x85. Birds beak isolation 16 of silicon oxide are also formed for isolation of devices. On top of the gate oxide layer 14, is then deposited a doped polysilicon layer 18 and a TiN layer 20, sequentially. The semiconductor structure 10 is then patterned and a polysilicon gate 22 with a titanium silicide layer 24 on top is then formed insulated by sidewall spacers 26 formed of a dielectric material of either SiO2 or Si3N4. This is shown in FIG. 1B. The LDD (lightly doped drain) implantation is performed in the source/drain regions 28, 30.
In the next step of the process, a cobalt layer 32 is blanket deposited on top of the semiconductor structure 10 by a technique such as sputtering. This is shown in FIG. 1C. The cobalt layer 32 and the silicon substrate 12 then reacts when annealed at a high temperature to form source/drain silicide layers 34, 36 of cobalt silicide, as shown in FIG. 1D. The unreacted cobalt layer 32 is then removed in a wet etch process with titanium silicide layer 24 remaining on the polysilicon gate 22. This is shown in FIG. 1E.
As shown in FIGS. 1Axcx9c1E, the most frequently used metal silicide material is TiSi2, however, other metal silicides such as CoSi2 and NiSi2 have also been used in forming polycide gates. The titanium silicide layer is normally formed by a two-stage annealing method. A thin layer of titanium is first sputtered or deposited by a chemical vapor deposition technique, or a titanium/silicon layer can be deposited by a co-sputtering technique. A first stage annealing process is then conducted at about 650xc2x0 C. such that titanium metal reacts with silicon substrate that it contacts to form titanium silicide. At this stage, the titanium silicide formed is the higher resistance value C49 phase. The unreacted titanium metal is then removed by a basic solution such as a solution of 5:1:1 DiW, 30% H2O2, NH4OH. During the same etching process, the silicon oxide surface layer formed is also removed. The semiconductor structure is then annealed in a second stage at 800xc2x0 C. in a nitrogen containing gas. During the second stage annealing, the titanium silicide of higher resistance value C49 phase is transformed to a lower resistance value C54 phase such that the lowest sheet resistance can be achieved.
In the conventional sidewall spacers 26 shown in FIG. 1E, the thickness is limited such that electrical shorting between the polysilicon gate 22 and the source/drain silicide 34, 36 frequently occurs. Such electrical shorting can cause serious damages to the semiconductor structure and thus greatly reduces its reliability.
It is therefore an object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate without the drawbacks or shortcomings of the conventional method.
It is another object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate wherein the spacers do not have a tapered shoulder region.
It is a further object of the present invention to provide a method for forming sidewall spacers on a polysilicon gate wherein the spacers are equipped with square shoulders.
It is another further object of the present invention to provide a method for forming sidewall spacers with square shoulders such that the possibility of electrical shorting between the polysilicon gate and the source/drain silicide is eliminated.
It is still another object of the present invention to provide a method for forming sidewall spacers with square shoulders on polysilicon gates by using a photoresist layer for shielding the sidewall spacers during the spacer formation process.
It is yet another object of the present invention to provide a semiconductor structure that has a polysilicon gate and a square-shouldered sidewall spacer surrounding the gate.
It is still another further object of the present invention to provide a semiconductor structure that has a polysilicon gate insulated by a square-shouldered sidewall spacer surrounding the gate and a source/drain silicide region.
It is yet another further object of the present invention to provide a semiconductor structure that has a polysilicon gate insulated by a square-shouldered sidewall spacer formed of SiO2, SiON or Si3N4.
In accordance with the present invention, a method for forming sidewall spacers with square shoulders on polysilicon gates and devices formed by the method are provided.
In a preferred embodiment, a method for forming sidewall spacers with square shoulders on polycide gates can be carried out by the operating steps of first providing a silicon substrate that has an active surface; depositing a polysilicon layer on the active surface of the substrate; depositing a first silicon nitride layer on the polysilicon layer; defining and forming a polysilicon gate with a silicon nitride pad on top; depositing a conformal silicon nitride layer overlaying the polysilicon gate and the silicon nitride pad; depositing a silicon oxide layer on top of the conformal silicon nitride layer; planarizing the silicon oxide layer until a top of the conformal silicon nitride layer is exposed; wet etching the conformal and the first silicon nitride layers exposing the polysilicon gate by using the silicon oxide layer as a photomask; coating a photoresist layer and etching-back such that only a cavity formed by the silicon oxide layer, the polysilicon gate and the conformal silicon nitride layer is filled with the photoresist; wet etching away the silicon oxide layer; and forming the square-shouldered sidewall spacers by a first anisotropic etching step for removing the first silicon nitride layer not masked by the photoresist layer and then by a second wet etching step removing the photoresist layer.
The method for forming sidewall spacers with square shoulders on polycide gates may further include the step of depositing the first silicon nitride layer to a thickness between about 1500 xc3x85 and about 5000 xc3x85, or the step of depositing the conformal silicon nitride layer to a thickness smaller than a thickness of the first silicon nitride layer, or the step of depositing the conformal silicon nitride layer to a thickness smaller than 1500 xc3x85. The method may further include the step of planarizing the silicon oxide layer by a chemical mechanical polishing technique. The method may further include the step of wet etching the conformal and the first silicon nitride layers by H3PO4. The first anisotropic etching step may be carried out by reactive ion etching or by plasma etching. The second wet etching step may be carried out by H2SO4/H2O2 wet etching.
The present invention is further directed to a semiconductor structure that includes a silicon substrate; a gate oxide layer on top of the silicon substrate; a polysilicon gate on the gate oxide layer; a metal silicide layer overlaying the polysilicon gate; and a square-shouldered sidewall spacer surrounding the polysilicon gate.
The semiconductor structure may further include a metal silicide layer overlaying a source region and a drain region of the semiconductor structure. The gate oxide layer may be less than 200 xc3x85 thick. The metal silicide may be selected from the group consisting of tungsten silicide, cobalt silicide, titanium silicide and tantalum silicide. The square-shouldered sidewall spacer may be formed of a dielectric material, or a material selected from the group consisting of SiO2, SiON and Si3N4. The metal silicide layer may be formed of a material selected from the group consisting of tungsten silicide, cobalt silicide, titanium silicide and tantalum silicide.